Number of time offsets allowed per port is limited by the tester specifications.
Hence, the patterns must be related to EVCD cycling clock to keep number of different offsets minimum.
For output ports, an output strobe is fired at appropriate offset from the starting of each vector to sample the output voltage at the port.
The sampled value is expected against the original value from the EVCD. CHANGES TO THE SIMULATION ENVIRONMENT: The pre silicon verification is mostly done with bottom-top approach.
Typical System Environment changes needed are mentioned below: Bypass PLLs: If possible, on chip PLLs can be altogether bypassed for functional testing.
This will drastically reduce the initialization time taken for each PLL, hence, saving the overall tester time.
This usually refers to verification of certain "parametric" values of the device.
These are device values specified and guaranteed by the device manufacturer.If PLLs cannot be altogether bypassed, it is better to provide all the reference clocks from test bench directly and bypass the internal generation of reference clocks.The intention of test here is to validate the logical functionality. Remove any fast simulation aid: To aid faster simulation, we employ various techniques like waiting for fewer numbers of cycles than that specified by the specifications.Similarly, for output ports, it determines where to sample, when to sample and what to expect using its own format. The first thing you would do is divide it into number of smaller but similar size timeslots. Similarly, for each vector, appropriate edge fires to drive the pattern.Hence, the EVCD needs to be converted to format that Tester understands. They along with additional information; specify information to drive/sample/expect for each signal for each timeslot. If there is no change in the signal value for a vector, there is no need to fire an edge.In system environment, the scenario is simulated and all the toggling at the DUT ports are captured in a particular format. VCD doesn’t directly provide the information regarding the direction for inout ports.